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RossComputerGuyRossComputerGuy
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feat(river_hdl): add data port writers
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‎packages/river_hdl/lib/river_hdl.dart‎

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@@ -8,6 +8,7 @@ export 'src/core/exec.dart';
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export 'src/core/fetcher.dart';
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export 'src/core/pipeline.dart';
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export 'src/core.dart';
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export 'src/memory/port.dart';
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export 'src/river_hdl_base.dart';
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// TODO: Export any libraries intended for clients of this package.

‎packages/river_hdl/lib/src/memory/port.dart‎

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import 'package:rohd/rohd.dart';
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import 'package:rohd_hcl/rohd_hcl.dart';
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/// A sized prefix data port writer to multiple output data ports.
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///
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/// Using multiple data ports for writing, this is capable of updating a memory
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/// model without reading first. This however does increase the circuit complexity
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/// due to having more duplicate lines. This is suitable when the memory model supports
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/// multiple data ports of different sizes.
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class SizedWriteMultiDataPort extends Module {
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SizedWriteMultiDataPort(
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Logic clk,
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Logic reset, {
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required DataPortInterface backingWriteByte,
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required DataPortInterface backingWriteHalf,
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required DataPortInterface backingWriteWord,
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DataPortInterface? backingWriteDword,
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required DataPortInterface source,
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}) {
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clk = addInput('clk', clk);
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reset = addInput('reset', reset);
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backingWriteByte = backingWriteByte.clone()
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..connectIO(
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this,
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backingWriteByte,
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outputTags: {DataPortGroup.control, DataPortGroup.data},
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inputTags: {DataPortGroup.integrity},
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uniquify: (og) => 'backingWriteByte_$og',
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);
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backingWriteHalf = backingWriteHalf.clone()
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..connectIO(
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this,
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backingWriteHalf,
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outputTags: {DataPortGroup.control, DataPortGroup.data},
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inputTags: {DataPortGroup.integrity},
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uniquify: (og) => 'backingWriteHalf_$og',
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);
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backingWriteWord = backingWriteWord.clone()
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..connectIO(
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this,
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backingWriteWord,
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outputTags: {DataPortGroup.control, DataPortGroup.data},
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inputTags: {DataPortGroup.integrity},
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uniquify: (og) => 'backingWriteWord_$og',
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);
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if (backingWriteDword != null) {
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backingWriteDword = backingWriteDword!.clone()
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..connectIO(
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this,
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backingWriteDword!,
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outputTags: {DataPortGroup.control, DataPortGroup.data},
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inputTags: {DataPortGroup.integrity},
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uniquify: (og) => 'backingWriteDword_$og',
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);
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}
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source = source.clone()
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..connectIO(
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this,
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source,
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outputTags: {DataPortGroup.control, DataPortGroup.integrity},
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inputTags: {DataPortGroup.data},
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uniquify: (og) => 'source_$og',
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);
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Sequential(clk, [
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If(
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reset,
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then: [
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source.done < 0,
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source.valid < 0,
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backingWriteByte.en < 0,
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backingWriteByte.addr < 0,
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backingWriteHalf.en < 0,
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backingWriteHalf.addr < 0,
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backingWriteWord.en < 0,
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backingWriteWord.addr < 0,
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if (backingWriteDword != null) ...[
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backingWriteDword!.en < 0,
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backingWriteDword!.addr < 0,
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],
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],
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orElse: [
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If(
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source.en,
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then: [
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Case(
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source.data.slice(6, 0),
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[
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CaseItem(Const(8, width: 7), [
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backingWriteByte.en < 1,
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backingWriteByte.addr < source.addr,
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backingWriteByte.data < source.data.slice(14, 7),
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source.done < backingWriteByte.done,
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source.valid < backingWriteByte.valid,
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]),
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CaseItem(Const(16, width: 7), [
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backingWriteHalf.en < 1,
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backingWriteHalf.addr < source.addr,
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backingWriteHalf.data < source.data.slice(22, 7),
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source.done < backingWriteHalf.done,
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source.valid < backingWriteHalf.valid,
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]),
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CaseItem(Const(32, width: 7), [
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backingWriteWord.en < 1,
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backingWriteWord.addr < source.addr,
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backingWriteWord.data < source.data.slice(38, 7),
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source.done < backingWriteWord.done,
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source.valid < backingWriteWord.valid,
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]),
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if (backingWriteDword != null)
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CaseItem(Const(64, width: 7), [
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backingWriteDword!.en < 1,
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backingWriteDword!.addr < source.addr,
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backingWriteDword!.data < source.data.slice(70, 7),
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source.done < backingWriteDword!.done,
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source.valid < backingWriteDword!.valid,
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]),
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],
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defaultItem: [
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source.done < 0,
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source.valid < 0,
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backingWriteByte.en < 0,
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backingWriteByte.addr < 0,
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backingWriteHalf.en < 0,
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backingWriteHalf.addr < 0,
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backingWriteWord.en < 0,
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backingWriteWord.addr < 0,
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if (backingWriteDword != null) ...[
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backingWriteDword!.en < 0,
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backingWriteDword!.addr < 0,
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],
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],
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),
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],
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orElse: [
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source.done < 0,
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source.valid < 0,
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backingWriteByte.en < 0,
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backingWriteByte.addr < 0,
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backingWriteHalf.en < 0,
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backingWriteHalf.addr < 0,
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backingWriteWord.en < 0,
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backingWriteWord.addr < 0,
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if (backingWriteDword != null) ...[
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backingWriteDword!.en < 0,
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backingWriteDword!.addr < 0,
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],
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],
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),
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],
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),
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]);
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}
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}
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/// A sized prefix data port writer to a single data port.
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///
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/// Using a single data port for reading & writing, this is capable of updating
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/// a memory model using the least amount of data ports. However, it performs a read
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/// before a write. This is suitable when the memory model does not suport multiple
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/// data ports of different sizes.
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class SizedWriteSingleDataPort extends Module {
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SizedWriteSingleDataPort(
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Logic clk,
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Logic reset, {
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required DataPortInterface backingRead,
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required DataPortInterface backingWrite,
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required DataPortInterface source,
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}) {
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clk = addInput('clk', clk);
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reset = addInput('reset', reset);
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if (backingRead.addr.width != backingWrite.addr.width) {
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throw 'Backing read & backing write must have the same address width';
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}
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if (backingRead.data.width != backingWrite.data.width) {
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throw 'Backing read & backing write must have the same data width';
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}
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if (source.data.width < 7) {
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throw 'Source port must be at least 7 bits to fit the width prefix';
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}
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if (backingRead.addr.width != source.addr.width) {
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throw 'Backing data ports and source port must have the same address width';
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}
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if (backingRead.data.width != (source.data.width - 7)) {
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throw 'Backing data ports and source port must have the same data width';
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}
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backingWrite = backingWrite.clone()
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..connectIO(
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this,
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backingWrite,
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outputTags: {DataPortGroup.control, DataPortGroup.data},
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inputTags: {DataPortGroup.integrity},
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uniquify: (og) => 'backingWrite_$og',
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);
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backingRead = backingRead.clone()
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..connectIO(
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this,
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backingRead,
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outputTags: {DataPortGroup.control},
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inputTags: {DataPortGroup.data, DataPortGroup.integrity},
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uniquify: (og) => 'backingRead_$og',
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);
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source = source.clone()
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..connectIO(
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this,
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source,
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outputTags: {DataPortGroup.control, DataPortGroup.integrity},
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inputTags: {DataPortGroup.data},
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uniquify: (og) => 'source_$og',
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);
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final width = source.data.width - 7;
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final value = source.data.slice(source.data.width - 1, 7);
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final dataSize = source.data.slice(6, 0).zeroExtend(width);
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final writeMask = Logic(name: 'writeMask', width: width);
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writeMask <=
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((Const(1, width: width) << dataSize) - Const(1, width: width));
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Sequential(clk, [
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If(
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reset,
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then: [
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source.done < 0,
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source.valid < 0,
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backingRead.en < 0,
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backingRead.addr < 0,
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backingWrite.en < 0,
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backingWrite.addr < 0,
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],
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orElse: [
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If(
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source.en,
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then: [
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backingRead.en < 1,
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backingRead.addr < source.addr,
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backingWrite.en < backingRead.done & backingRead.valid,
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backingWrite.addr < source.addr,
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backingWrite.data <
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((backingRead.data & ~writeMask) | (value & writeMask)),
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source.done < backingRead.done & backingWrite.done,
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source.valid < backingRead.valid & backingWrite.valid,
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],
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orElse: [
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source.done < 0,
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source.valid < 0,
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backingRead.en < 0,
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backingRead.addr < 0,
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backingWrite.en < 0,
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backingWrite.addr < 0,
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],
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),
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],
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),
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]);
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}
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}

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