target: cortex-m: fix support for arv8m caches

Align to upstream code that always flushes the caches if they are
present, without checking if the caches are enabled.

Signed-off-by: HAOUES Ahmed <ahmed.haoues@st.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Antonio Maria BORNEO <antonio.borneo@foss.st.com>

Author: ahmed-haoues

src/target/armv7m_cache.c

@@ -150,6 +150,7 @@ static int armv7m_identify_cache_internal(struct target *target)
 
 		// separate d or unified d/i cache at this level ?
 		if (ctype & (CLIDR_CTYPE_UNIFIED_CACHE | CLIDR_CTYPE_D_CACHE)) {
+			cache->has_d_u_cache = true;
 			cache->arch[cl].d_u_size = decode_ccsidr(d_u_ccsidr[cl]);
 
 			LOG_TARGET_DEBUG(target,
@@ -167,6 +168,7 @@ static int armv7m_identify_cache_internal(struct target *target)
 		}
 
 		if (ctype & CLIDR_CTYPE_I_CACHE) {
+			cache->has_i_cache = true;
 			cache->arch[cl].i_size = decode_ccsidr(i_ccsidr[cl]);
 
 			LOG_TARGET_DEBUG(target,
@@ -306,7 +308,6 @@ static int armv7m_cache_helper(struct target *target, const char *helper,
 
 int armv7m_d_cache_flush(struct target *target, uint32_t address,
 	unsigned int length)
-
 {
 	struct armv7m_common *armv7m = target_to_armv7m(target);
 	struct armv7m_cache_common *cache = &armv7m->armv7m_cache;
@@ -315,23 +316,17 @@ int armv7m_d_cache_flush(struct target *target, uint32_t address,
 	if (retval != ERROR_NOT_IMPLEMENTED)
 		return retval;
 
-	if (!cache->info_valid)
-		return ERROR_OK;
-
-	if (target->state != TARGET_HALTED) {
-		LOG_TARGET_ERROR(target, "not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	if (!armv7m->armv7m_cache.d_u_cache_enabled)
+	if (!cache->info_valid || !cache->has_d_u_cache)
 		return ERROR_OK;
 
 	uint32_t line_len = cache->d_min_line_len;
 	uint32_t addr_line = ALIGN_DOWN(address, line_len);
 	uint32_t addr_end = address + length;
 
 	while (addr_line < addr_end) {
-		mem_ap_write_u32(armv7m->debug_ap, DCCIMVAC, addr_line);
+		retval = mem_ap_write_u32(armv7m->debug_ap, DCCIMVAC, addr_line);
+		if (retval != ERROR_OK)
+			return retval;
 		addr_line += line_len;
 		keep_alive();
 	}
@@ -349,23 +344,17 @@ int armv7m_i_cache_inval(struct target *target, uint32_t address,
 	if (retval != ERROR_NOT_IMPLEMENTED)
 		return retval;
 
-	if (!cache->info_valid)
-		return ERROR_OK;
-
-	if (target->state != TARGET_HALTED) {
-		LOG_TARGET_ERROR(target, "not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	if (!armv7m->armv7m_cache.i_cache_enabled)
+	if (!cache->info_valid || !cache->has_i_cache)
 		return ERROR_OK;
 
 	uint32_t line_len = cache->i_min_line_len;
 	uint32_t addr_line = ALIGN_DOWN(address, line_len);
 	uint32_t addr_end = address + length;
 
 	while (addr_line < addr_end) {
-		mem_ap_write_u32(armv7m->debug_ap, ICIMVAU, addr_line);
+		retval = mem_ap_write_u32(armv7m->debug_ap, ICIMVAU, addr_line);
+		if (retval != ERROR_OK)
+			return retval;
 		addr_line += line_len;
 		keep_alive();
 	}

src/target/armv7m_cache.h

@@ -39,12 +39,12 @@ struct armv7m_arch_cache {
 struct armv7m_cache_common {
 	bool info_valid;
 	bool defer_identification;
+	bool has_i_cache;
+	bool has_d_u_cache;
 	unsigned int loc;					// level of coherency
 	uint32_t d_min_line_len;			// minimum d-cache line_len
 	uint32_t i_min_line_len;			// minimum i-cache line_len
 	struct armv7m_arch_cache arch[6];	// cache info, L1 - L7
-	bool i_cache_enabled;
-	bool d_u_cache_enabled;
 };
 
 int armv7m_identify_cache(struct target *target);

src/target/cortex_m.c

@@ -895,14 +895,10 @@ static int cortex_m_debug_entry(struct target *target)
 		secure_state ? "Secure" : "Non-Secure",
 		target_state_name(target));
 
-	if (armv7m->armv7m_cache.info_valid) {
-		armv7m->armv7m_cache.d_u_cache_enabled = ccr & CCR_DC_MASK;
-		armv7m->armv7m_cache.i_cache_enabled = ccr & CCR_IC_MASK;
-
+	if (armv7m->armv7m_cache.info_valid)
 		LOG_TARGET_DEBUG(target, "D-Cache %s, I-Cache %s",
-			armv7m->armv7m_cache.d_u_cache_enabled ? "enabled" : "disabled",
-			armv7m->armv7m_cache.i_cache_enabled ? "enabled" : "disabled");
-	}
+			(ccr & CCR_DC_MASK) ? "enabled" : "disabled",
+			(ccr & CCR_IC_MASK) ? "enabled" : "disabled");
 
 	if (armv7m->post_debug_entry) {
 		retval = armv7m->post_debug_entry(target);