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@chipsalliance

CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

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  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.7k 1.2k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.8k 276

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

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  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

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  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 749 180

Repositories

Showing 10 of 117 repositories
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 25 Apache-2.0 56 146 (6 issues need help) 41 Updated Apr 8, 2026
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 146 Apache-2.0 95 227 (10 issues need help) 77 Updated Apr 8, 2026
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,628 Apache-2.0 651 352 (1 issue needs help) 149 Updated Apr 8, 2026
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    SystemVerilog 43 796 0 0 Updated Apr 8, 2026
  • caliptra-dpe Public

    High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

    chipsalliance/caliptra-dpe’s past year of commit activity
    Rust 21 Apache-2.0 32 18 8 Updated Apr 8, 2026
  • i3c-core Public
    chipsalliance/i3c-core’s past year of commit activity
    SystemVerilog 46 Apache-2.0 24 10 2 Updated Apr 8, 2026
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 9 6 0 0 Updated Apr 8, 2026
  • chips-alliance-website Public
    chipsalliance/chips-alliance-website’s past year of commit activity
    SCSS 5 MIT 7 8 2 Updated Apr 8, 2026
  • caliptra-infra Public

    Various tools used for Caliptra's Continuous Integration flows

    chipsalliance/caliptra-infra’s past year of commit activity
    SystemVerilog 2 Apache-2.0 5 5 2 Updated Apr 8, 2026
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 371 ISC 88 45 (4 issues need help) 23 Updated Apr 7, 2026
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