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Pull requests: chipsalliance/verible

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Pull requests list

Add --alignment_group_boundary flag to control alignment group splitting
#2501 opened Mar 28, 2026 by sjalloq Loading…
2
Fix module-level alignment breaking after non-alignable constructs
#2500 opened Mar 27, 2026 by dannyoler Loading…
3 tasks
1
fix issue 2288: add --rules=+generate-label-prefix=prefix:A_ to change the style_regex
#2498 opened Mar 21, 2026 by ddppt-yy Loading…
1
1
Modernize use of bison and flex in a more elaborate rule.
#2497 opened Mar 17, 2026 by hzeller Collaborator • Draft
1
Added support for token concatenation
#2488 opened Jan 21, 2026 by sifferman Loading…
1
Add inlay hint support for Verilog module instantiations
#2487 opened Jan 18, 2026 by ya-uhs Loading…
1
Add TextMate Grammar for Verilog/SystemVerilog Highlighting
#2472 opened Nov 25, 2025 by clysto Loading…
7
Replaced clang-cl for MSVC Compiler on Windows
#2460 opened Oct 1, 2025 by corco Collaborator • Draft
1
Update bison.bzl and flex.bzl to work with Bazel 8
#2452 opened Aug 29, 2025 by mneilly Loading…
4
Disable --//bazel:use_local_flex_bison that won't work with bazel 8
#2449 opened Aug 26, 2025 by hzeller Collaborator • Draft
1
Resolve "Non ANSI-C style input,output port declaration Verilog code linter issue"
#2447 opened Aug 22, 2025 by matlupi • Draft
5
Simplify settings of warnings.
#2386 opened Apr 7, 2025 by hzeller Collaborator • Draft
Enhanced Alignment Options for Verilog Formatter
#2368 opened Mar 23, 2025 by ButterSus • Draft
2
fix: #2171
#2314 opened Dec 25, 2024 by Bhavin-umatiya Loading…
7
fixe #2278
#2312 opened Dec 24, 2024 by Bhavin-umatiya Loading…
8
Add VSCode command of generating verible.filelist at the root folder
#2277 opened Oct 5, 2024 by Hamster5295 Loading…
3
Resolve "Rejected valid signal name"
#2102 opened Feb 6, 2024 by matlupi Loading…
1
6
Enable suspicious-semicolon_rule by default
#2066 opened Dec 21, 2023 by IEncinas10 Collaborator Loading…
2
Provide autofixes for always_ff_non_blocking_rule
#1912 opened May 8, 2023 by IEncinas10 Collaborator Loading…
2 of 3 tasks
25
Added an always_wrap_module_instantiations flag want-merge-needs-rebase a pull request that should not be lost, but needs rebasing first.
#1909 opened May 5, 2023 by jbylicki Collaborator Loading…
1
5
Format preprocessed token stream in multiple passes want-merge-needs-rebase a pull request that should not be lost, but needs rebasing first.
#1898 opened Apr 28, 2023 by kbieganski Collaborator Loading…
16
[WIP] adding exit code to the preprocessor
#1533 opened Nov 16, 2022 by karimtera Contributor • Draft
4
[VeriblePreProcessor][5]: White-spaces support in "VerilogPreprocess" class.
#1376 opened Aug 4, 2022 by karimtera Contributor Loading…
1
[WIP] Verible standalone preprocessor
#1360 opened Jul 10, 2022 by karimtera Contributor Loading…
3 of 6 tasks
18
[WIP] TokenPartitionTree refactoring / "Choice" nodes support
#1328 opened Apr 30, 2022 by mglb Contributor • Draft
1
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